1. Field of the Invention
The present invention relates to sense-amplifier circuits. More particularly, the present invention relates to a fast dynamic mirror sense amplifier with separate comparison, equalization and evaluation paths.
2. The State of the Art
In order to correctly read the data item from a memory cell from a memory matrix, it is known to compare the data item read from the memory matrix cell with the data item read from a reference matrix cell, so as to detect the difference between a programmed cell and an erased cell. For this purpose, memory matrices are usually preset so that a reading of the data item from a memory cell is matched by a reading of an amount of current that flows across a reference matrix cell. The difference between the two readings determines the particular data item read.
A first possible implementation is to use a local reference memory cell for each sense amplifier as illustrated in FIG. 1. Reference memory cell 10 is biased by n-channel MOS transistor 12 in cascode configuration using inverter 14 fed by diode-connected p-channel MOS transistor 16 used as a current source. The current drawn by p-channel MOS transistor 16 is mirrored to p-channel MOS transistor 20, which sources current to matrix memory cell 18 through n-channel MOS transistor 22 in cascode configuration using inverter 24. During an equalization period of timely length, pass gate 26 is enabled and is used to charge the MAT node 28 to the potential of the REF node 30. At the end of the equalization period, pass gate 26 is turned off and the MAT node 28 is allowed to move toward either the power supply potential or ground potential depending on the difference between the reference cell current and the matrix cell current. The sense operation is performed by a comparator 32, having the nodes REF and MAT as its inputs.
The approach of FIG. 1 has the disadvantage of causing disturbs on the REF node, both during the equalization period and the subsequent sense period. At the beginning of the equalization period the MAT node 28 is grounded and, after the pass gate 26 has been enabled, it is directly connected to the REF node 30, whose transient is in this way disturbed. Considering that the gate of the p-channel MOS transistor 20 at REF node 30 is an input of the comparator 32, inevitably, during the evaluation period, the commutation of the output couples a disturb onto it and, consequently, disturbs the reference current.
Moreover having many reference cells is disadvantageous both from the point of view of die area occupation and from the point of view of managing these reference cells during testing operations.
A normal evolution of the system illustrated in FIG. 1 consists of locally repeating the reference cell current for each sense amplifier by using a local current mirror as shown in FIG. 2. The same reference-current-generating structure shown in FIG. 1 is used in the system of FIG. 2, employing reference cell 10, n-channel MOS transistor 12 in cascode with inverter 14 and p-channel MOS transistor current source 16. The current drawn by the reference memory cell 10 is mirrored from p-channel MOS transistor 16 to p-channel MOS mirror transistor 34. Diode-connected n-channel MOS transistor 36 establishes the REF_N voltage.
To eliminate the disturbs during the equalization and the evaluation periods, the circuit of FIG. 2 makes use of additional local current mirrors to generate two reproductions of the REF_P node (EQ_LEV and COMP_LEV) to be used for the equalization and as reference input of the comparator 32. Local current mirror structures 38, 40, and 42 each employ a p-channel MOS transistor (shown as 38-1, 40-1, and 42-1, respectively, in mirror structures 38, 40, and 42) and an n-channel MOS transistor (shown as 38-2, 40-2, and 42-2, respectively, in mirror structures 38, 40, and 42) to generate the signals REF_P, EQ_LEV, and COMP_LEV. P-channel MOS mirror transistor 20 and n-channel MOS transistor 22 cascoded with inverter 24 provide a mirrored current for matrix memory cell 18 as in the circuit of FIG. 1. The EQ_LEV voltage is supplied to the MAT node input to comparator 32 through pass gate 46.
In a system that uses the architectural approach of FIG. 2, the p-channel MOS mirror transistor 38-1 in local current mirror 38 must be set to precisely the reference cell current because, during the evaluation period, the voltage on the node MAT will increase or decrease depending on the difference between the matrix cell current and the current biasing the p-channel MOS mirror transistor 38-1. The EQ_LEV and COMP_LEV signals are obtained in the same way, starting from the reference cell current, using local current mirrors 40 and 42 identical to local current mirror 38 used to generate REF-P signal.
In systems like that shown in FIG. 2, the REF-N node supplies three different subcircuits, multiplied by the number of sense amplifiers, and thus has a very high capacitive load.